As the level of semiconductor device integration grows, functional testing becomes an increasingly costly process. Complete functional verification of a complex integrated circuit is often impossible unless specific design methodologies are established to enhance the testability of the device. Many of the commonly accepted enhancement methods are based on the use of serial test patterns to exercise and monitor portions of the devices's internal logic. The complications associated with the test procedures and test system hardware needed to support these methods can be minimized if pseudo random test patterns are used to stimulate the device, and if signature analysis is used to compress many device response patterns into a single pattern, or signature.
Traditional deterministic testing requires the test system to store and manipulate many thousand of test patterns which describe both the device stimulus and expected response. This is accomplished with massive pattern memories and complex pattern sequence controllers, both of which contribute significantly to the costs of the test system. As LSI And VLSI devices become increasingly complex, these traditional test methods are becoming less effective for functional verification.
Functional verification is greatly enhanced by incorporating "scan paths" in the device design. Although various implementations exist, scan paths basically provide serial ports through which the device can be exercised and monitored. This enhances internal observability without adding eternal device test points (pins), except for the scan in/out pins. In this case, fewer parallel test patterns may be required, however the test system must be able to store and manipulate long serial test patterns.
A pseudo random serial scan test system is disclosed in IEEE INTERNATIONAL TEST CONFERENCE PROCEEDINGS, 1983 (ISBN 0-8186-0502-2, IEEE Catalog No. 1 83CH1933-1, Computer Society No. 502, Library of Congress No. 83-81805, pp. 283-287). The described test system is basically a modified conventional test system with a configurable (Linear Feedback Shift Registers) LFSR for pseudo random pattern generation, and a parallel input LFSR for signature analysis. Both LFSR's are shared resources, i.e. the serial pattern has to be addressed to be multiplexed. The signature comparison appears to be made with software.